800Mhz FSB

Lemme try this again.

Since asking this question I've gained a little more information, but here's the original question:


800Mhz FSB
I've been looking through some of the threads and although this has been asked, there are no answers posted. In reference to the P4 800Mhz FSB, these are what I know to be true (so far today ).

The 200Mhz DDR Ram is quad-pumped to 800Mhz, producing the advertised speeds. If this is true, then more questions come to mind.

I'm in process of shopping for my parts to build a new super-system. Most of today's DDR Ram is peaked out at 400Mhz and available in Dual-Channel sets. Looking past the fact that there is no such thing "dual channel memory" only "matched" sets, I have to ask this question. If the Maximum FSB is 800Mhz by means of quad-pumping the DDram, what purpose does this new DDR3200 (400Mhz) memory serve?

If my math is correct and the quad-pumping is constant, the system would slow my DDR3200 to 200Mhz, negating the reason for purchasing the ram in the first place.

I have found only this one specific document that -almost- addresses this question (http://www.intel.com/design/Pentium4/prodbref/), but need much more information. Can anyone help here?


So here's the update: I've been told by Giga-byte that PC2700(266Mhz FSB) DDRam will also run at the advertised 800Mhz. Can I be safe inassuming that the minimum requirements would essentially be 200Mhz FSB memory?

Please help if you can.

 

This might help you a bit:

http://www.techwarelabs.com/reviews/processors/intel_800mhz_fsb/index_2.shtml

Daddad

 

From Adrian's Rojok Pot:


"These DDR chips actually run at 200MHz but they have been internally widened to deliver a single 2n-bits wide (where n is a number) data transfer per clock cycle. This is different from standard SDRAM which only deliver one n-bit wide data transfers per clock cycle.

At the I/O pins however, the single 2n-bit wide data transfer is split into two n-bit wide, half clock cycle data transfers. The two pieces of data are then transferred to the memory controller on both the rising and falling edges of the signal. This differs from normal SDRAM which only carries data on the rising edge of the signal.

In short, the internal DRAM core had been redesigned to allow twice as much data to reach the I/O pins in a single clock cycle. The data is then split up so that half of it is transmitted via the rising edge of the signal while the other half is carried by the falling edge of the signal.

Because twice as much data is being transferred per clock cycle, manufacturers and end-users alike continue to label 200MHz DDR SDRAM as 400MHz DDR SDRAM. "